Edge-AI applications necessitate the joint application of hardware acceleration and software optimization to meet energy and area constraints. However, the co-design of these systems is hindered by the lack of integration options for novel hardware prototypes offered by commonly employed Machine Learning frameworks. Bridging this gap, we present HEEPstor, an open-hardware co-design framework that enables the deployment of quantized, PyTorch-defined models on heterogeneous RISC-V systems interfacing custom accelerators. We demonstrate its application by executing quantized ML models for image classification on a X-HEEP platform integrating tailored systolic arrays, showcasing its flexibility for hardware-software explorations.