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  4. Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing
 
research article

Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing

Kheradmand Boroujeni, Bahman  
•
Piguet, Christian  
•
Leblebici, Yusuf  
2011
Journal of Low Power Electronics
  • Details
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Type
research article
DOI
10.1166/jolpe.2011.1137
Author(s)
Kheradmand Boroujeni, Bahman  
Piguet, Christian  
Leblebici, Yusuf  
Date Issued

2011

Published in
Journal of Low Power Electronics
Volume

7

Issue

2

Start page

285

End page

293

Subjects

low-power design

•

variability

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSM  
LAP  
Available on Infoscience
September 4, 2011
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/70671
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