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  4. System and method for removing scalloping and tapering effects in high aspect ratio through-silicon vias of wafers
 
patent

System and method for removing scalloping and tapering effects in high aspect ratio through-silicon vias of wafers

Frasca, Simone  
•
Charbon, Edoardo  
•
Carrara, Sandro  
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2021

A method for manufacturing vias in a silicon wafer, the silicon wafer having a <110> crystal orientation, and having a <111> plane that is perpendicular to a surface of the wafer, tilted by 35.26°, the method comprising the steps of providing a mask having a rhomboidal-shaped opening onto a surface of the silicon wafer, such that edges of the rhomboidal-shaped opening line up with a <111> plane of a crystalline structure of the silicon wafer, etching a hole in the silicon wafer at the rhomboidal-shaped opening, and polishing the hole after the etching by a anisotropic etching.

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Type
patent
EPO Family ID

78411702

Author(s)
Frasca, Simone  
Charbon, Edoardo  
Carrara, Sandro  
Leghziel, Rebecca  
TTO classification

TTO:6.2031

EPFL units
AVP-R-TTO  
AQUA  
ICLAB  
DOICountry codeKind codeDate issued

US11735478

US

B2

2023-08-22

US2021351075

US

A1

2021-11-11

Available on Infoscience
December 3, 2021
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/183464
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