System and method for removing scalloping and tapering effects in high aspect ratio through-silicon vias of wafers
A method for manufacturing vias in a silicon wafer, the silicon wafer having a <110> crystal orientation, and having a <111> plane that is perpendicular to a surface of the wafer, tilted by 35.26°, the method comprising the steps of providing a mask having a rhomboidal-shaped opening onto a surface of the silicon wafer, such that edges of the rhomboidal-shaped opening line up with a <111> plane of a crystalline structure of the silicon wafer, etching a hole in the silicon wafer at the rhomboidal-shaped opening, and polishing the hole after the etching by a anisotropic etching.
78411702
TTO:6.2031
Patent number | Country code | Kind code | Date issued |
US11735478 | US | B2 | 2023-08-22 |
US2021351075 | US | A1 | 2021-11-11 |