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patent

Fin field-effect transistor (finfet) based semiconductor memory array having memory cells with a reduced surface area

Giterman, Robert  
•
Burg, Andreas  
•
Yigit, Halil Andac  
2024

A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitline contact in connection with the first fin, and a storage node contact in connection with the first fin, and a read transistor having a storage node gate over a second fin, the storage node gate connected to a storage node gate contact, the storage node gate contact connected to the storage node contact, a read wordline contact in connection with the second fin, and a read bitline contact in connection with the second fin, wherein the write wordline gate and the storage node gate are arranged in series to each other along an extension axis that coincides with an longitudinal axis of the write wordline gate and a longitudinal axis of the storage node gate.

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Type
patent
EPO Family ID

87571706

Author(s)
Giterman, Robert  
Burg, Andreas  
Yigit, Halil Andac  
Note

Alternative title(s) : (de) Fin-feldeffekttransistor (finfet)-basierte halbleiterspeicheranordnung mit speicherzellen mit reduzierter oberfläche (fr) Matrice de mémoire semi-conductrice à transistor à effet de champ à ailettes (finfet) ayant des cellules de mémoire avec une surface réduite

IdentifierCountry codeKind codeDate issued

EP4326024

EP

A3

2024-05-29

US2024062811

US

A1

2024-02-22

EP4326024

EP

A2

2024-02-21

Available on Infoscience
March 4, 2024
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/205752
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