Chabloz, J.Ruffieux, D.Enz, C.2010-06-242010-06-242010-06-242008https://infoscience.epfl.ch/handle/20.500.14299/51091In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic is proposed. By cascading compact dual-modulus divider slice with recursive feedback mechanisms, any dividing ratio is easily implemented. A 5-stages 0.18 mum CMOS implementation demonstrates a power consumption factor as low as 235 nW/MHz under 1.2 V supply for high dividing ratios.text::conference output::conference proceedings::conference paper