A 10-to-12 GHz 5mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Gong, JiangSebastiano, FabioCharbon, EdoardoBabaie, Masoud2021-03-262021-03-262021-03-262020-01-0110.1109/RFIC49505.2020.9218380https://infoscience.epfl.ch/handle/20.500.14299/176509WOS:000612019100004This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of -258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves -65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 mu W frequency tracking loop is also introduced to robustly lock the CSPLL to a 100MHz reference. Fabricated in 40-nm CMOS, the 0.13mm(2) CSPLL achieves an RMS jitter of 50 fsec at 11.4GHz while consuming 5mW.Engineering, Electrical & ElectronicTelecommunicationsEngineeringcharge-sampling pllcharge-sampling phase detectorlow-jitterdivider-less frequency tracking loopA 10-to-12 GHz 5mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spurtext::conference output::conference proceedings::conference paper