Akkaya, AyçaÇelik, FiratLeblebici, Yusuf2021-01-162021-01-162021-01-16202010.1109/ISCAS45731.2020.9180941https://infoscience.epfl.ch/handle/20.500.14299/174742WOS:000706854700124This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacitors, splitting monotonic capacitor switching, and dynamic SAR memory to optimize both power consumption and SAR loop delay using a single comparator. Measurement results show that the 9-bit SAR ADC achieves 47.6 dB SNDR and 29.6 fJ/conversion-step figure-of-merit (FoM) near Nyquist frequency at 222 MS/s, consuming 1.07 mA from a 1.2 V supply. The ADC does not consume static power and the current consumption scales down linearly with the sampling rate, keeping the low FoM value constant over a very wide sampling frequency range. The design occupies an active area of 92 μm × 180 μm (0.017 mm 2 ) in 65 nm CMOS.text::conference output::conference proceedings::conference paper