Zhang, LeyuRen, YuqingShen, YifeiZhou, WuyangBalatsoukas-Stimming, AlexiosZhang, ChuanBurg, Andreas2025-01-262025-01-262025-01-25202410.1109/ISCAS58744.2024.105581522-s2.0-85198560700https://infoscience.epfl.ch/handle/20.500.14299/244586In this paper, we describe a frame-interleaving hardware architecture for a generalized node-based successive cancellation list (SCL) decoder. By efficiently reusing otherwise idle computational units, two independent frames can be decoded simultaneously, resulting in a significant throughput gain. Based on this new architecture, we also exploit graph ensembles to diversify the decoding, enhancing the error-correcting performance by 0.28 dB and reducing the worst-case latency for serial graph processing by over 32%. Implementation results show that the proposed SCL decoder with frame-interleaving architecture achieves a throughput of 7.15 Gbps and an area efficiency of 37.63 Gbps/mm2, which is 1.56× and 1.11× better than the state-of-the-art node-based SCL decoders.falseframe-interleavinghardware architecturePolar codessequence repetition (SR) nodesuccessive cancellation list (SCL) decodingtext::conference output::conference proceedings::conference paper