A Power-Efficient LVDS Driver Circuit in 0.18-μm CMOS Technology

Tajalli, ArminLeblebici, Yusuf2007-06-212007-06-212007-06-21200710.1109/RME.2007.4401832https://infoscience.epfl.ch/handle/20.500.14299/9176WOS:000255548900037This article presents a power-efficient and low-voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption low, a new technique has been applied to control the output voltage slew. A pre-driver circuit is also utilized to have a very low total equivalent input capacitance of 50 fF. Designed in 0.18 μm CMOS technology, the entire output driver circuit including the input pre-driver, draws only 5.6 mArms while the output voltage swing is VOD = 400 mV and the other specs are compliant with the LVDS requirements.CMOS integrated circuitsLVDS output driverLow powerOutput driverOutput bufferA Power-Efficient LVDS Driver Circuit in 0.18-μm CMOS Technologytext::conference output::conference proceedings::conference paper