Harel, OdemCasarrubias, Emmanuel NietoEggimann, ManuelGurkaynak, FrankBenini, LucaTeman, AdamGiterman, RobertBurg, Andreas2022-07-182022-07-182022-07-182022-01-0110.1109/LSSC.2022.3182531https://infoscience.epfl.ch/handle/20.500.14299/189314WOS:000815659800001Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access limitations. In this letter, we present a GC-eDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells and also integrates a replica bit line for optimal access timing to improve performance and power consumption. A 64- kB GC-eDRAM macro was fabricated in a 65- nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 mu s retention time.Computer Science, Hardware & ArchitectureEngineering, Electrical & ElectronicComputer ScienceEngineeringedramembedded memorygain cellrefreshretention timesramsystem architectureembedded dram macro3t gain-cellsramtext::journal::journal article::research article