Ghanaatian, RezaWidmer, MarcoBurg, Andreas2022-04-112022-04-112022-04-112022-04-0110.1109/MDAT.2021.3081687https://infoscience.epfl.ch/handle/20.500.14299/186954WOS:000766265600019This article presents a design-for-test methodology for embedded memories. The methodology relies on a fully random fault model of post-fabrication errors, which results in a low-overhead test strategy. The methodology's effectiveness is demonstrated on an embedded system with faulty memories.Computer Science, Hardware & ArchitectureEngineering, Electrical & ElectronicComputer ScienceEngineeringrandom access memorycircuit faultsreliabilitystatisticsembedded systemsmeasurementreliability engineeringnanometer nodesapproximate computingfaulty memoriesquality-yield analysistext::journal::journal article::research article