Levisse, Alexandre Sébastien JulienGaillardon, Pierre-Emmanuel Julien MarcGiraud, BastienO'Connor, IanNoel, Jean PhilippeMoreau, MathieuPortal, Jean-Michel2019-01-072019-01-072019-01-072018-12-2110.1109/TNANO.2018.2887140https://infoscience.epfl.ch/handle/20.500.14299/153352With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar resistive random access memories (RRAM) appear to be one of the most promising technologies. However, when organized in 1 or 2-transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance, and reliability issue during reset operation. The association of multiple-independent-gate polarity controllable transistors (PCT) with RRAM overcomes these drawbacks while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations, and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) and are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2 V versus more than 2 V in 1T1R bitcells), thus reducing selector reliability concerns. We also propose an innovative programming strategy that takes advantage of the PCT polarity control and enables 500× improvement in reset performance. Finally, the proposed bitcells perform 15%–67% faster than CMOS bitcells in read.Embedded memorybipolar RRAMOxRAMpolarity controllable transistorsSiNWFET1T1R2T1RLogic gatesTransistorsSwitchesNonvolatile memoryProgrammingSemiconductor device modelingCMOS technologytext::journal::journal article::research article