Lo Conte, F.Pastre, M.Saliese, J. M.Krummenacher, F.Kayal, M.2010-10-212010-10-212010-10-21200810.1109/NEWCAS.2008.4606341https://infoscience.epfl.ch/handle/20.500.14299/55922WOS:000262463700036This paper presents a compact- and a macro-model for estimating and simulating the perturbations induced in the substrate by high-voltage transistors switching inductive loads. On one hand, it allows the designer to predict the amount of switching noise generated by a particular topology. On the other hand, it enables a wise choice of the positioning of sensitive low-voltage circuits around the noisy devices, as well as the choice of appropriate shielding structures. The models proposed are validated by measurements on a prototype circuit at 25°C. © 2008 IEEE.Integrated circuit modelingNoise couplingPower parasitic modelingPower semiconductor devicesSubstrate modelingtext::conference output::conference proceedings::conference paper