Harel, OdemYigit, AndacFeifel, ElianaGiterman, RobertBurg, AndreasTeman, Adam2025-01-252025-01-252025-01-25202410.1109/JSSC.2024.34897932-s2.0-85210289563https://infoscience.epfl.ch/handle/20.500.14299/244418Gain-cell embedded dynamic random access memory (GC-eDRAM) has emerged as a suitable choice for embedded memory implementation due to its high density, low leakage current, and voltage scaling compatibility. This work presents a 16-kB 3T-1C GC-eDRAM macro, featuring an innovative internal reference voltage generation mechanism and an on-chip dc-dc converter for internal boosted supply generation. The memory architecture is partitioned to efficiently accommodate the reference generation and implement a variation-tolerant sensing scheme. The on-chip dc-dc converter is employed for internally generating a boosted voltage that enhances charge retention to increase the data retention time (DRT). The memory macro was implemented in a 65-nm CMOS technology and fabricated as part of a research test chip. Measurements across a spectrum of boosted voltages and different temperature points, show a significant improvement in DRT compared with similar GC-eDRAM designs, without compromising area, performance, or power dissipation.falseEmbedded dynamic random access memory (eDRAM)embedded memorygain cellinternal voltageretention timesensingstatic random access memory (SRAM)text::journal::journal article::research article