Temiz, YükselGuiducci, CarlottaLeblebici, Yusuf2013-01-112013-01-112013-01-11201310.1109/TCPMT.2012.2228004https://infoscience.epfl.ch/handle/20.500.14299/87759WOS:000324384600003This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple alternative to spincoated resist. Unlike conventional photolithography methods, the technique allows resist patterning on very high topography, and therefore chip-level photolithography can be done without using any wafer reconstitution approach. Moreover, this paper proposes a via sidewall passivation method which eliminates dielectric etching at the bottom of the via and simplifies the whole integration process. In this paper, two 50-μm-thick chips were post-processed, aligned, bonded, and connected by Cu TSVs, which have parylene sidewall passivation. Daisy-chain resistance measurements show 0.5 ohm resistance on average for 60-μm-diameter TSVs, with a yield of more than 99% for 1280 TSVs from five different chip stacks. Subsequently, the techniques were applied to CMOS microprocessor stacking as a test vehicle. Die-level post-CMOS processing for 40-μm-diameter via etching, redistribution layer patterning, and chip-to-chip bonding were successfully demonstrated with the real chips.3-D IntegrationDie-level processingDry-film lithographyParylene bondingPost-Complementary Metal Oxide Semiconductor (CMOS) processingThrough-Silicon Via (TSV)via-last TSVtext::journal::journal article::research article