An, HyochanSchiferl, SamVenkatesan, SiddharthWesley, TimZhang, QiruiWang, JingchengChoo, Kyojin D.Liu, ShiyuLiu, BowenLi, ZiyunGong, LuyaoZhong, HengfeiBlaauw, DavidDreslinski, RonaldKim, Hun SeokSylvester, Dennis2022-04-012022-04-012022-04-01202010.1109/JSSC.2020.3041858https://infoscience.epfl.ch/handle/20.500.14299/186843We propose an ultra-low-power (ULP) image signal processor (ISP) that performs on-the-fly in-processing frame compression/decompression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence. This approach reduces energy consumption spent processing and transmitting unimportant image data to achieve a 16 × imaging system energy gain in an intruder detection scenario. The ISP was fabricated in 40-nm CMOS and consumes only 170 μW at 5 frames/s for neural network-based intruder detection and 192 × compressed image recording.Deep neural network (DNN)energy-efficient processorevent recognitionimage compressionimage signal processor (ISP)text::journal::journal article::research article