Case Study of Fault-Tolerant Architectures for 90nm CMOS Cryptographic Cores

Stanisavljevic, MilosGürkaynak, Frank KaganSchmid, AlexandreLeblebici, YusufGabrani, Maria2007-06-262007-06-26200710.1109/RME.2007.4401860https://infoscience.epfl.ch/handle/20.500.14299/9353WOS:000255548900064This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been applied. One of the fault-tolerant architectures is a novel four-layer architecture exhibiting a large immunity to permanent as well as random failures. Characteristics of the averaging/ thresholding layer are emphasized. Measurement results show advantage of four-layer architecture over triple modular redundancy in terms of reliability.fault-tolerant architecturesAES crypyographic corefour-layer architecturetriple modular redundancyCase Study of Fault-Tolerant Architectures for 90nm CMOS Cryptographic Corestext::conference output::conference proceedings::conference paper