Zwicky, StefanBenkeser, ChristianBurg, Andreas PeterHuang, Qiuting2013-06-032013-06-032013-06-03201310.1109/ICASSP.2013.6638111https://infoscience.epfl.ch/handle/20.500.14299/92540Modern wireless communication systems require efficient channel equalizer implementations. This paper explores the design space of reduced-state sequence estimation (RSSE). We show how the concept of pre-computation can be applied to greatly reduce computational complexity, such that efficient RSSE architectures can be derived. As a proof of concept, an RSSE was implemented in dedicated hardware, that achieves a 1.6 times higher hardware efficiency when compared to prior art.Channel equalizationRSSEDesign space explorationEvolved EDGEVLSI implementationEfficient VLSI Implementation of Reduced-State Sequence Estimation for Wireless Communicationstext::conference output::conference proceedings::conference paper