High-Level Synthesis through Transforming VHDL Models, System-on-Chip Methodologies & Design Languages

Prihozhy, Anatoly2006-06-142006-06-142006-06-14200110.1007/978-1-4757-3281-8_12https://infoscience.epfl.ch/handle/20.500.14299/231199LTS3High-Level Synthesis through Transforming VHDL Models, System-on-Chip Methodologies & Design Languagestext::book/monograph::book part or chapter