Eberli, S.Burg, A.Boesch, T.Fichtner, W.2011-06-062011-06-062011-06-062007https://infoscience.epfl.ch/handle/20.500.14299/68387WOS:000257110900268This paper describes the implementation of the complete baseband processing of an IEEE 802.11a receiver on a design-framework for application specific processors. The underlying generic architecture is described, the computational kernels required for an IEEE 802.11a receiver are analyzed, and suitable processing units and architecture-configurations, to be defined at design-time, are identified. The discussion of the receiver implementation shows that the proposed architecture can meet real-time requirements on a 0.13 mu m CMOS process using a dock frequency of 160 MHz. The design demonstrates how the proposed standard-specific reconfigurable architecture is a valid alternative to ASIC and DSP implementations when looking for a balance between performance and flexibility.Ofdmtext::conference output::conference proceedings::conference paper