Meinerzhagen, Pascal AndreasAndersson, O.Sherazi, Y.Burg, Andreas PeterRodrigues, J.2011-11-202011-11-202011-11-20201110.1109/ECCTD.2011.6043593https://infoscience.epfl.ch/handle/20.500.14299/72669Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-V T analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-VT regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized at nominal supply voltage. Both analysis methods are able to predict the energy minimum supply voltage (EMV) of any given design. Next, the results of a sub-V T synthesis at EMV using re-characterized SCLs are compared to the initial synthesis results. Finally, the results of timing-driven synthesis in both the above-VT and the sub-VT domain are compared to the results of power-driven synthesis.text::conference output::conference proceedings::conference paper