Maneux, CMukherjee, C.Deng, M.Dubourg, M.Reveil, L.Bordea, G.Lecestre, A.Larrieu, G.Trommer, J.Breyer, E.T.Slesazeck, S.Mikolajick, T.Baumgartner, O.Karner, M.Pirker, D.Stanojevic, Z.Atienza Alonso, DavidLevisse, Alexandre Sébastien JulienAnsaloni, GiovanniPoittevin, A.Bosio, A.Deleruyelle, D.Marchand, C.O'Connor, I2021-11-012021-11-012021-11-01202110.1109/IEDM19574.2021.9720572https://infoscience.epfl.ch/handle/20.500.14299/182650This paper presents the set of simulation means used to develop the concept of N2C2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation, compact modeling and EM simulation are leveraged through a Design- Technology Co-Optimization (DTCO) to achieve innovative 3D circuit architectures. Further, System-Technology Co-Optimization (STCO) implications on 3D NN system architecture are explored.text::conference output::conference proceedings::conference paper