Fey, GoerschwinGhasempouri, TaraJacobs, SwenMartino, GianlucaRaik, JaanRiener, Heinz2019-06-182019-06-182019-06-182018-01-0110.1109/VLSI-SoC.2018.8644732https://infoscience.epfl.ch/handle/20.500.14299/157749WOS:000462970000036We present an outline of the field of Design Understanding and summarize state-of-the-art research in deriving human-understandable knowledge in form of logic properties from an unknown design.Engineering, Electrical & ElectronicEngineeringdesign understandingtemporal logicsspecificationverificationsynthesisassertionspropertiestext::conference output::conference proceedings::conference paper