Najmzadeh, M.Tsuchiya, Y.Bouvet, D.Grabinski, W.Ionescu, A. M.2013-12-092013-12-092013-12-09201310.1016/j.mee.2013.02.003https://infoscience.epfl.ch/handle/20.500.14299/97749WOS:000326003600055In this paper, we report formation of GAA buckled dual Si nanowire MOSFETs including two sub-80 nm Si cores on bulk Si using 0.8 mu m optical lithography and local oxidation for the first time. 0.833 GPa uniaxial tensile stress is measured in the buckled suspended dual Si nanowires using micro-Raman spectroscopy. The array of GAA buckled dual Si nanowire MOSFETs at V-DS = 50 mV shows 64 mV/dec. subthreshold slope and 61% stress-based low-field electron mobility enhancement in comparison to the omega-gate relaxed reference device. Finally, digital logic implementation is demonstrated using multi-gate nanowires on bulk Si. (C) 2013 Elsevier B.V. All rights reserved.Multi-gateSi nanowireLocal oxidationStrained SiMicro-Raman spectroscopyTransport enhancementLogictext::journal::journal article::research article