Shokrollahi, AminCarnelli, DarioFox, JohnHofstra, KlaasHolden, BrianHormati, AliHunt, PeterJohnston, MargaretKeay, JohnPesenti, SergioSimpson, RichardStauffer, DavidStewart, AndySurace, GiuseppeTajalli, ArminTalebi Amiri, OmidTschank, AntonUlrich, RogerWalter, ChristophLicciardello, FabioMogentale, YohanSingh, Anant2016-11-232016-11-232016-11-23201610.1109/ISSCC.2016.7417967https://infoscience.epfl.ch/handle/20.500.14299/131598High-speed signaling over package substrates is key to delivering the promise of 2.5D integration. Applications abound and include high-density memory interfaces, sub-division of large dies to increase yield and lower development time, sub-division of a die to achieve upward or downward scalability, or connecting to an off-chip SerDes or optics engine. Each of these in-package applications typically has high throughput and onerously low power constraints along with a low-loss channel. Several solutions have been proposed. Interposer substrates [1], or Chip-on-Substrate-on-Wafer [2] allow for very high-density wiring and low power using CMOS transceivers. Their high manufacturing and testing cost makes them prohibitive for anything but high-end applications. A different approach using high-speed ground-referenced single-ended signaling is reported in [3], which is intended for shorter channels up to 4.5mm and a BER of 1e-12. An approach using differential signaling on up to 0.75" of Megtron 6 material and a BER of 1e-9 is reported in [4]. A comparison is given in Fig. 10.1.1.algoweb_electronicsintegrated circuit packagingSerDes technologiesChord signalingtext::conference output::conference proceedings::conference paper