Akarvardar, K.Eggimann, C.Tsamados, D.Chauhan, Y.Wan, G. C.Ionescu, A. M.Wong, H. S.-P.2010-11-082010-11-082010-11-08200710.1109/DRC.2007.4373670https://infoscience.epfl.ch/handle/20.500.14299/57257Analytical Modeling of the Suspended-Gate FET and Design Insights for Digital Logictext::conference output::conference proceedings::conference paper