Marakkalage, Dewmini SudaraDe Micheli, Giovanni2023-04-062023-04-062023-04-062023-04-1710.23919/DATE56975.2023.10137314https://infoscience.epfl.ch/handle/20.500.14299/196722In logic circuits, the number of fanouts a gate can drive is limited, and such limits are tighter in emerging technologies such as superconducting electronic circuits. In this work, we study the problem of resynthesizing a logic network with bounded-fanout gates while minimizing area. We 1) formulate this problem for a fixed target logic depth as an integer linear program (ILP) and present exact solutions for small logic networks, and 2) propose a top-down approach to construct a feasible solution to the ILP which yields an efficient algorithm for fanout bounded synthesis. When using the minimum depth achievable with unbounded fanouts as the target logic depth, our top-down approach achieves 11.82% better area as compared to the stateof-the-art with matching or better delays.fanout-bounded synthesisinteger linear programemerging technologiestext::conference output::conference proceedings::conference paper