Jackson, Brad R.Mazzilli, FrancescoSaavedra, Carlos E.2010-05-132010-05-132010-05-13200910.1109/TMTT.2009.2017250https://infoscience.epfl.ch/handle/20.500.14299/50079WOS:000266040900008A new odd-order frequency multiplier topology is demonstrated in this work that uses a subharmonic mixer to realize a frequency tripler. A feedforward circuit is used for fundamental cancellation at the output and eliminates the need for filtering structures. For demonstrative purposes, and to validate the concept, a 1-3-GHz proof-of-concept frequency tripler circuit was fabricated. The tripler circuit achieved a measured output fundamental suppression of up to 30 dB below the third harmonic and a conversion gain of up to 3 dB. The circuit was implemented in CMOS 0.18-mu m technology and the chip area was 0.8 mm(2) including bonding pads.CMOS analog integrated circuitsfrequency conversionfrequency triplermonolithic microwave integrated circuits (MMICs)subharmonic mixer (SHM)Barrier-VaractorCmosDesigntext::journal::journal article::research article