Camus, VincentSchlachter, JérémyEnz, ChristianGautschi, MichaelGurkaynak, Frank2016-09-292016-09-292016-09-29201610.1109/ESSCIRC.2016.7598342https://infoscience.epfl.ch/handle/20.500.14299/129581WOS:000386656300113The floating-point unit is one of the most common building block in any computing system and is used for a huge number of applications. By combining two state-of-the-art techniques of imprecise hardware, namely Gate-Level Pruning and Inexact Speculative Adder, and by introducing a novel Inexact Speculative Multiplier architecture, three different approximate FPUs and one reference IEEE-754 compliant FPU have been integrated in a 65 nm CMOS process within a low-power multi-core processor. Silicon measurements show up to 27% power, 36% area and 53%power-area product savings compared to the IEEE-754 single-precision FPU. Accuracy loss has been evaluated with a high-dynamic-range image tone-mapping algorithm, resulting in small but non-visible errors with image PSNR value of 90 dB.FPUApproximate CircuitsApproximate ComputingArithmetic CircuitsCircuit PruningSpeculative AdderSpeculative Multipliertext::conference output::conference proceedings::conference paper