Rassekh, AminJazaeri, FarzanSallese, Jean-Michel2022-06-202022-06-202022-06-202022-01-0110.1109/TNANO.2022.3174471https://infoscience.epfl.ch/handle/20.500.14299/188569WOS:000803344100002Relying on the previously developed charge-based approaches, this paper presents a physics-based design space of negative capacitance in double-gate and bulk MOSFET architectures. The impact of thickness variation of the ferroelectric on the DC characteristics has been deeply investigated. The model precisely estimates a critical thickness of ferroelectric at instability conditions before the device goes into the hysteresis regime. Explicit relationships have been driven for hysteresis voltages which can be used as a general guideline for technology optimization of negative capacitance FETs.Engineering, Electrical & ElectronicNanoscience & NanotechnologyMaterials Science, MultidisciplinaryPhysics, AppliedEngineeringScience & Technology - Other TopicsMaterials SciencePhysicslogic gatescapacitancemosfetelectric fieldssemiconductor device modelinghysteresisinsulatorscharge-based modelmosfetnegative capacitanceinstabilityhysteresisgate junctionless fetsdrain currentmodelmosfetchargesmfistext::journal::journal article::research article