Harb, HassanAl Ghouwayel, Ali ChamasConde-Canencia, LauraMarchand, CedricBoutillon, Emmanuel2022-08-012022-08-012022-08-012022-07-2210.1007/s11265-022-01795-yhttps://infoscience.epfl.ch/handle/20.500.14299/189602WOS:000828958200001This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10(-3).Computer Science, Information SystemsEngineering, Electrical & ElectronicComputer ScienceEngineeringchannel codingdecoder implementationasicnon-binary ldpcmin-sumparity checklow-complexitynonbinarycodesarchitecturedesigntext::journal::journal article::research article