El Ghouli, SalimRideau, DenisMonsieur, FredericScheer, PatrickGouget, GillesJuge, AndrePoiroux, ThierrySallese, Jean-MichelLallement, Christophe2018-01-152018-01-152018-01-15201810.1109/Ted.2017.2772804https://infoscience.epfl.ch/handle/20.500.14299/143992WOS:000418753200002Transconductance efficiency (g(m)/I-D) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of g(m)/I-D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultra-thin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the g(m)/I-D-based design methodologies usage in DG FDSOI transistors sizing.Analog and RFdouble-gate (DG) FETsfully depleted Silicon-on-Insulator (FDSOI)low powertransconductance efficiencyultrathin body and box (UTBB)text::journal::journal article::research article