Sans, M.Burg, A.Fichtner, W.Acunto, G.2011-06-062011-06-062011-06-06200210.1109/ACSSC.2002.1196950https://infoscience.epfl.ch/handle/20.500.14299/68347WOS:000182548900203In this work, we present an improved version of an ASIC implementation of the adaptive arithmetic coding algorithm which uses a two-level memory hierarchy. We propose algorithmic modifications and a special hardware structure to speed-up the design without degrading the compression ratio obtained using this memory hierarchy. Moreover, several new features which increase the compression efficiency are introduced. Finally, a VLSI implementation based on the results of our work is presented.text::conference output::conference proceedings::conference paper