Tajalli, ArminGurkaynak, Frank K.Leblebici, YusufAlioto, MassimoBrauer, Elizabeth J.2008-03-072008-03-072008-03-07200810.1109/ISCAS.2008.4541375https://infoscience.epfl.ch/handle/20.500.14299/19906WOS:000258532100038This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) in an SCL gate by a factor close to two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultralow power applications. Designed in conventional digital 0.18um CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.Source-coupled logic (SCL)Current-mode logic (CML)SubthresholdPower-delay productSubthreshold SCL (STSCL)Ultra-low-powertext::conference output::conference proceedings::conference paper