Elakhras, AyatallahGuerrieri, AndreaJosipovic, LanaIenne, Paolo2023-07-032023-07-032023-07-032022-01-0110.1109/FPL57034.2022.00046https://infoscience.epfl.ch/handle/20.500.14299/198678WOS:000975890500034High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in some important use-cases. Nevertheless, the literal conversion of a standard compiler's control-data flow graph into elastic circuits often produces circuits with notable resource demands and inferior performance. In this work, we present a methodology for generating more area- and timing-efficient elastic circuits. We show that our strategy results in significant area and timing improvements compared to previous circuit generation strategies.Computer Science, Hardware & ArchitectureComputer Science, Software EngineeringComputer Science, Theory & MethodsComputer Sciencetext::conference output::conference proceedings::conference paper