Tajalli, ArminLeblebici, Yusuf2008-11-202008-11-202008-11-20200910.1109/JSSC.2008.2010788https://infoscience.epfl.ch/handle/20.500.14299/31366WOS:000263032100020This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation in low supply voltages using a conventional 0.18um CMOS technology feasible. The output driver circuit consumes 4.5mA while driving an external 100-Ohm resistor with an output voltage swing of VOD = 400mV, achieving a normalized power dissipation of 3.42mW/Gbps. The area of the LVDS driver circuit is 0.067mm2 and the measured output jitter is sigma_{rms} = 4.5ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5Gbps where the speed will be limited by the load RC time constant.CMOS integrated circuitsCurrent-mode logic (CML)Low-voltage differential signaling (LVDS)Output driverSource-coupled logic (SCL)text::journal::journal article::research article