Arcamone, JPérez-Murano, Fvan den Boogaart, M A FBrugger, J2006-03-202006-03-202006https://infoscience.epfl.ch/handle/20.500.14299/228873For the purpose of integrating nanomechanical structures with CMOS circuitry, nanostencil lithography ensures parallel patterning for rapid processing at wafer scale and nanometer-sized features definition. Moreover, this patterning technique is compatible with CMOS substrates given that it does not alter circuitry performance. However, a major limitation in nanostencil lithography is gap-induced pattern blurring naturally occurring if a planar stencil is used in combination with a substrate containing topography (e.g. CMOS). This phenomenon has been characterized and a corrective technique is implemented in order to eliminate the blurring.text::report