Boukhayma, AssimKraxner, AndreaCaizzone, AntoninoYang, MinhaoBold, DanielEnz, Christian2022-09-122022-09-122022-09-122022-01-0110.1109/JEDS.2022.3200520https://infoscience.epfl.ch/handle/20.500.14299/190628WOS:000849253700001This paper compares two in-pixel source follower stage designs for low noise CMOS image sensors embedded both on a same 5 mm by 5 mm chip fabricated in a 180 nm CIS process. The presented chip embeds two pixel variants, one based on a body-effect-canceled thin oxide PMOS and the other embeds a native thick oxide NMOS. On the other hand they share the same sense node, same amplification circuit and 11 bit single slope analog to digital converter (SS-ADC). The imager characterization demonstrates a histogram peak noise of 0.34 e(RMS)(-) with the PMOS SF pixel and 0.47 e(RMS)(- )with the NMOS SF at maximum analog gain. This performance is obtained at room temperature and 119 frame per second. Both pixel variants demonstrate a full well capacity over 5600 electrons.Engineering, Electrical & ElectronicEngineeringcmos4tcisconversion gainsub-electron noisewide dynamictext::journal::journal article::research article