Pathak, KaranSaid HamdiouiAnsaloni, GiovanniKlein, JoshuaGeorgi GaydadjievZapater, MarinaAtienza, David2025-06-062025-06-062025-06-052025-06-0410.1145/3737876https://infoscience.epfl.ch/handle/20.500.14299/251089Full-System (FS) simulation is essential for performance evaluation of complete systems that execute complex applications on a complete software stack consisting of an operating system and user applications. Nevertheless, they require careful fine-tuning against real hardware to obtain reliable performance statistics, which can become tedious, error-prone, and time-consuming with typical trial-and-error approaches. We propose a novel, streamlined, component-level calibration methodology to address these shortcomings to validate FS simulation models. Our methodology greatly accelerates the validation process without sacrificing accuracy. It is Instruction Set Architecture (ISA)-agnostic, and can tackle hardware specifications at different levels of detail. We demonstrate its effectiveness by validating FS models against both open-hardware and IP-protected (closed hardware) RISC-V silicon, achieving a mean error of 19-23% for the SPEC CPU2017 suite in the two cases. We introduce the first open-source RISC-V-based FS-validated simulation models with a complete and replicable methodology.enFull SystemArchitectural Simulator\RISC-VValidated Modelstext::journal::journal article::research article