A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Kull, LukasToifl, ThomasSchmatz, MartinFrancese, P. A.Menolfi, C.Braendli, M.Kossel, M.Morf, T.Meyer Andersen, T.Leblebici, Yusuf2013-03-122013-03-122013-03-122013https://infoscience.epfl.ch/handle/20.500.14299/90267An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate clocking for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC stacks the capacitive SAR DAC (CDAC) with the reference capacitor to reduce the area and enhance the settling speed. It achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm2 in 32nm CMOS SOI technology.SAR ADCtime-interleavedlow-powerhigh-speedA 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOStext::conference output::conference proceedings::conference paper