Speed/Power/Area Trade-offs for High Speed Inter Layer Data Transmission in 3D Stacked ICs

Leblebici, YusufDe Micheli, GiovanniBeanato, Giulia2014-08-182014-08-18201410.5075/epfl-thesis-6278https://infoscience.epfl.ch/handle/20.500.14299/105867urn:nbn:ch:bel-epfl-thesis6278-1en3D ICsThrough Silicon Vias TSVsChip Multi-Processors CMPshigh speed serial linksSpeed/Power/Area Trade-offs for High Speed Inter Layer Data Transmission in 3D Stacked ICsthesis::doctoral thesis