Xu, HuPavlidis, VasileiosDe Micheli, Giovanni2010-01-152010-01-152010-01-152009https://infoscience.epfl.ch/handle/20.500.14299/45572A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used for 2-D interconnects. Simulation results show that the proposed approach decreases the total wire delay up to 42% as compared to conventional approaches. The complexity of the proposed algorithm is linear to the number of planes that the wire spans.3-D ICsRepeater insertionOn-chip interconnectTiming optimizationtext::conference output::conference paper not in proceedings