Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography

Sacchetto, DavideXie, ShenqiSavu, Andreea VeronicaZervas, MichailDe Micheli, GiovanniBrugger, JürgenLeblebici, Yusuf2011-07-282011-07-282011-07-282011https://infoscience.epfl.ch/handle/20.500.14299/69840Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithographytext::conference output::conference proceedings::conference paper