Oliva, NicolòCasu, Emanuele AndreaCavalieri, MatteoIonescu, Mihai Adrian2020-01-242020-01-242020-01-242018-10-1110.1109/ESSDERC.2018.8486867https://infoscience.epfl.ch/handle/20.500.14299/164898We propose and experimentally demonstrate double-gated n-type WSe 2 FETs with excellent top gate high-k dielectric layer. Under back gate control, the devices behave as n-type enhancement transistors, with ON/OFF current ratios larger than 6 orders of magnitude and a ON current close to 1 pA/μm under a drain bias of 100 mV. Negative top gate biases determine a much steeper turn-on of the back gated transfer characteristic and a reduction of the hysteresis. Top gated device behaves as n-type depletion FETs, exhibiting a I ON /I OFF ratio larger than 10 6 under positive bias applied to the back gate. A minimum hysteresis of 40 mV and an average subthreshold slope close to 100 mV/dec prove the high quality of the deposited top gate dielectric. The electron mobility has been extracted using the Y-function method, obtaining 22.15 cm 2 V -1 s -1 under a drain bias of 1 mV.text::conference output::conference proceedings::conference paper