A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Kull, LukasToifl, T.Schmatz, M.Francese, P. A.Menolfi, C.Braendli, M.Kossel, M.Morf, T.Meyer Anderson, T.Leblebici, Yusuf2013-11-262013-11-262013-11-262014https://infoscience.epfl.ch/handle/20.500.14299/97280A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step. High conversion speed of up to 100GS/s and high input bandwidth of 22GHz is achieved by using a 1:64 interleaver with integrated sampling. Single NMOS transistors followed by 1:4 demux stages are used to sample the signal. Skew and gain adjustment is implemented on-chip. The ADC consumes 667mW at 90GS/s and 845mW at 100GS/s and can be operated from a single supply voltage. It is implemented in 32nm SOI CMOS and occupies 0.45mm2.SARADCtime-interleavedSOICMOSA 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOStext::conference output::conference proceedings::conference paper