Biswas, ArnabDagtekin, NilayGrabinski, WladyslawBazigos, AntoniosRoyer, Cyrille LeHartmann, Jean-MichelTabone, ClaudeVinet, MaudIonescu, Mihai Adrian2014-02-242014-02-242014-02-24201410.1063/1.4867527https://infoscience.epfl.ch/handle/20.500.14299/101131WOS:000332729200045In this work we report experimental results on the use of Tunnel Field-Effect Transistors (TFET) as capacitorless Dynamic Random Access Memory (DRAM) cells, implemented as a double-gate (DG) Fully-Depleted Silicon-On-Insulator (FD-SOI) devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) with a total overlap of the back gate over the channel region (LG+LIN). A potential well is created by biasing the back gate (VBG) in accumulation while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+i junction and stored in the electrically induced potential well.Tunnel FETCapacitorless memoryDRAM1 Transistor memorytext::journal::journal article::research article