Atienza Alonso, DavidBeretta, Ivan2014-04-032014-04-03201410.5075/epfl-thesis-6142https://infoscience.epfl.ch/handle/20.500.14299/102520urn:nbn:ch:bel-epfl-thesis6142-9enHigh-level synthesisIterative stencil loopsMulti-core SoCsWireless sensor networksModel-based designKnowledge-driven designDesign Methodologies for Application-Oriented Embedded Systems Under Variable Performance/Constraints Tradeoffsthesis::doctoral thesis