Tasselli, GabrieleWang, BanGhamari, SaeedRobert, ChristianBotteron, CyrilFarine, Pierre-André2012-11-012012-11-012012-11-01201210.1109/NEWCAS.2012.6329057https://infoscience.epfl.ch/handle/20.500.14299/86442WOS:000310372500117This paper deals with the development of a four-channel low-power Phased Array Front-End (PhA-FE) at 24 GHz, targeting both low-power radar sensors and battery powered transceiver applications. Typically, PhA-FEs are power hungry architectures due to multiple parallel RF channels in the FE and complex algorithms for beam steering or high bit-rate demodulation in the digital part. In contrast, we target in this paper applications where both beam steering algorithms and data demodulation are relatively simple and hence achievable with low-power digital signal processing. More specifically, we report on four significant building blocks of the architecture, a Low Noise Amplifier (LNA), a Vector Modulator Phase Shifter (VMPS), a Quadrature Voltage Controlled Oscillator (QVCO) and an Analogue to Digital Converter (ADC) that have been designed the first three in 90nm and the last in 180nm CMOS technology. The LNA shows 24.4 dB gain, 3.4 dB NF and −24.4 dBm input P1dB. The single quadrant VMPS has more than 90° of phase control range and shows less than 0.7 dB of gain variation over phase shifting. The QVCO which consumes less than 32mW, buffer included, has a tuning range of 8%. The 6bit 20 MS/s ADC consumes 1.8mW.text::conference output::conference proceedings::conference paper