Xu, H.Pavlidis, V.De Micheli, G.2010-02-112010-02-112010-02-112010https://infoscience.epfl.ch/handle/20.500.14299/46618A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used for 2-D interconnects. Simulation results show that the proposed approach decreases the total wire delay up to 42% as compared to conventional approaches. The complexity of the proposed algorithm is linear to the number of planes that the wire spans.3-D ICsrepeater insertionon-chip interconnecttiming optimizationtext::conference output::conference poster not in proceedings