Convertino, C.Zota, C. B.Baumgartner, Y.Staudinger, P.Sousa, M.Mauthe, S.Caimi, D.Czornomaz, L.Ionescu, A. M.Moselund, K. E.2020-08-132020-08-132020-08-132019-01-0110.1109/IEDM19573.2019.8993610https://infoscience.epfl.ch/handle/20.500.14299/170811WOS:000553550000176We present scalable III-V heterojunction tunnel FETs fabricated using a Si CMOS-compatible FinFET process flow and integrated on Si (100) substrates. The tunneling junction is fabricated through self-aligned selective p(+) GaAsSb raised source epitaxial regrowth on an InGaAs channel. Similarly, the drain is formed by an n(+) InGaAs regrowth. The Si CMOS-compatible fabrication process includes a self-aligned replacement metal gate module, high-k/metal gate, scaled device dimensions and doped extensions, enabling high junction alignment accuracy. The devices exhibit a minimum subthreshold slope of 47 mV/decade, an ION of 1.5 mu A/mu m at I-OFF = 1 nA/mu m and V-DD = 0.3 V, and I-60 of 10 nA/nm. This is the first demonstration of sub-60 mV/decade switching in heterostructure TFETs on Si (100), showing the strong promise of the technology for future advanced logic nodes aiming at low-power applications.text::conference output::conference proceedings::conference paper